S'	R'	Present State Q	Next State Q	Next State Q'
0	0	X	1	1
0	1	X	1	0
1	0	X	0	1
1	1	Q	Q	Q'

Note: The state of S'=0 and R'=0 is forbidden. For S'=1 and R'=1, the output remains in the previous state.

Note: The state of S=1 and R=1 is forbidden. For S=0 and R=0, the output remains in the previous state.
 

Inputs		Outputs
D	G	Q	Q'
L	H	L	H
H	H	H	L
X	L	Qo	Qo'

• Latches - No Isolation - (7475)
• Leading Edge Flip-flop - Isolation - (7474)
• Trailing Edge Flip-flop - Isolation - (74LS112)
• Master-Slave Flip-flop - Isolation - (74107)

In this case, the flip-flop is trailing edge triggered.

The Setup time is non-zero.(The out put of the gates can be affected before the critical edge)

The Hold time is zero.(The output of the gates cannot be affected before the critical edge)

Timing Diagram for the 74LS112