ece 291 - Lecture Z

ECE291

Computer Engineering II

Plavcan, Summer 1997

Lecture Z

Today's Topics

Bus I/O, DMA

Description of DMA
DMA hardware
DMA modes
DMA cycle
Coding for DMA
DSP on Sound Blaster

What is DMA?

DMA stands for Direct Memory Access

Uses same Address/Data lines on ISA bus
Controls the ISA bus instead of the processor ("bus master")
Does not require the processor for data transfer
Devices which use DMA:

Floppy Drive (DRQ2)
Hard Drive (varies)
Sound Card (varies)

DMA vs. Progammed I/O

Requires less processor load
Can continually transfer the same block (loop indefinitely)
Devices which are demand-based can be serviced more efficiently

DMA characteristics:

8-bit or 16-bit transfers

DMA Hardware (8237 DMAC)

The PC has two 8237 DMA Controllers, arranged in a Master/Slave organization:

Processor has HOLD/HOLD Acknowledge lines to interact with 8237

DMAC can gain control of ISA bus by asserting HOLD
Processor acknowledges with HLDA

DRQ4 services slave controller

Priorities are set ast fixed

DRQ0 highest,DRQ7 lowest
Set at POST
Can be reprogrammed for rotating priority

ISA address/data/control lines are also connected (not shown)

Can access control registers through ports
Each channel has a page register associated with it

DMA Controller	Slave				Master
DRQ#	0	1	2	3	4	5	6	7
Memory Address Register I/O Address	00h	02h	04h	06h	C0h	C4h	C8h	CCh
Page Register	87h	83h	81h	82h	(none)	8Bh	89h	8Ah
Count Register I/O Address	1	3	5	7	(none)	C6h	CAh	CEh

DMA Controller Slave Master

Control Register I/O Address 08h D0h

Mode Register I/O Address 0Bh D6h

Mask Register I/O Address 0Ah D4h

Clear Byte F/F I/O Address 0Ch D8h

8237 Modes

Intel 8237 can be set to four differnt style of transfer:

Single - One transfer at a time, allow processor access to the bus between transfers
Block - Transfer all data, do not allow processor acces to the bus (may cause problems with memory refresh!!!)
Demand - Keep transferting as long as target keeps DRQ asserted
Cascade - allow a slave controller use of the DMAC (used for DRQ4)

In addition, the DMA controller can be set to make continuous transfers

known as auto-initialized DMA
normal DMA is known as "single-cycle"

8237 is clocked at 1/2 of ISA Bus (.5 *BLCK)

up to 4.166MHz (8.33 Mhz ISA)
Maximum transfer rate: 4.166MB/s (16-bit DMA)
Maximum Programmed I/O transfer rate: 2.77 MB/s

Size of transfer

Master can only generate word-sized transfers
Slave can generate byte-sized transfers
Minumum transfer size: 1 byte
Maximum transfer size: 64KB (8-bit),128KB (16-bit)

Page Register

Because the range of the 8237 is 64K bytes (or 64k words), each channel has a page register to extend the address to 24-bits
We use real mode, so we only use 4 bits of the page register
To get the page #, we calculate our linear (absolute) address. The upper 4 bits are the page:

DMA Cycle

Single-mode DMA cycle:

End of DMA transfer

TC assterted
DMAC releases bus to processor (HOLD deasserted)
Target Device generates IRQ to signal processor

Coding DMA Transfers

Programming the DMA controller is not a simple process, but it can be reduced to the following steps:

Find the Page and Page Offset of the memory block you wish to transfer
Turn off the DMA channel (so it win't accept requests while you reprogram it)
Clear the byte pointer flip/flop
Write the transfer mode to the mode register
Write the page offset to the address register
Write the length (-1 byte/word) to the count register
(0=1 byte, 65535=64Kbytes)
Write the page # to the page register
Re-enable the DMA channel
Set up target device

; Code to convert segment:offset to page:page_offset
;
; SI contains offset,
; DX contains segment
:

   mov ax,dx
   mov cl,4
   shl ax,cl                ; shift segment left 4 
   shr dx,cl                ; shift segment right 12
   add si,ax                ; add shifted segment to offset
   adc dh,0

; Now SI contains the offset within the page, 
; the low 4-bits of DH contain the page #

; Disable the DMA channel so we can set it
   mov ax,channel
   and ax,3                  ; channel mod 4
   or ax,MODE                ; set mode bits
   out MASKREG,al            ; write DMA mode

; Clear byte ptr F/F
   out BYTEREG,al                 ; any value to reset

; write mode to mode register
   mov al, mode
   out MODEREG,al

; write page offset to address reg.
   mov ax,si                 ; get offset in ax
   out ADDRREG,al            ; write LSB of DMA offset
   mov al,ah                 
   out ADDRREG,al            ; write MSB of DMA offset

; write length (-1) to count reg.
   mov ax,length             ; ax=length-1
   dec ax                    ;
   out COUNTREG,al           ; write LSB of size
   mov al,ah                 
   out COUNTREG,al           ; write MSB of size

; write page# to page register
   mov al,dh
   out PAGEREG,al            ; write page

; re-enable the channel
   mov ax,channel
   and al,3                  ; channel mod 4
   out MASKREG,al            ; enable sound card DMA

; now set up the target device...

Sound Blaster DSP

Creative Lab's SoundBlaster (and all other compatible cards) use DMA to transfer information between memory and the DSP (digital signal/sound processor) on the card. Modern sound cards support multiple DMA channels (for 16-bit transfers, and multiple record/playback for digital effects processing). The sound card can play sounds in the background without loading the system.

See Lecture X for more details on how to program the SoundBlaster.

See "ISA System Architecture" (Tom Shandley / Don Anderson, Mindshare Press) for more information on DMA.

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