ECE 411

This course is an intensive introduction to the fundamentals of computer architecture. Relying heavily upon the elementary principles taught in ECE 290 and ECE 390 (old ECE 291), we will discuss the basic design, or architecture, of computing hardware. Computer systems involve architecture design at many levels. We will focus on the instruction set architecture (ISA) level (the interface between the software and computing hardware) and the microarchitecture level (the computing hardware itself). We will examine to some extent, the level above the instruction set (the programming language level) and the level below the microarchitecture (the logic gate level) in order to deepen our understanding of computing systems. This course has a demanding design component; you will implement some of the basic concepts presented in lecture using real hardware design tools.

Instructor

Wen-mei Hwu
Office: 215 CSL
E-Mail: w-hwu-at-csrd.illinois.edu

Teaching Assitants

Daniel Manjarres (manjarrs-at-illinois.edu)
Dean Glazeski (dean.glazeski-at-gmail.com)
Anthony Brown (anbrown2-at-illinois.edu)

Lecture

106B1 Engineering Hall
Tuesday and Thursday
2:00pm - 3:20pm

Instructor Office Hours

215 CSL

Day	Hours
Monday	None
Tuesday	10:00 - 11:00am
Wednesday	None
Thursday	10:00 - 11:00am
Friday	None
Saturday	None

Course TA Office Hours*

252 EL (EWS) is the main location. We may ask you to meet us at the Grainger Library if 252 EL gets overcrowded.

Anthony Brown

Day	Hours
Monday	3:30 - 4:30pm
Tuesday	None
Wednesday	3:30 - 4:30pm
Thursday	None
Friday	3:30 - 4:30pm
Saturday	None

Dean Glazeski

Day	Hours
Monday	10:00 - 11:00am
Tuesday	None
Wednesday	9:30 - 10:30am
Thursday	None
Friday	10:00 - 11:00am
Saturday	None

* subject to change

Prerequisites

ECE 290 (or equivalent) and ECE 291 (new ECE 390, or equivalent)

Text

Computer Organization and Design: The Hardware/Software Interface, 3rd Edition - John Hennessy, David Patterson

Other Useful Books

High-Performance Computer Architecture, 3rd Edition - Harold S. Stone
Structured Computer Organization, 4th Edition - Andrew Tanenbaum
The Student's Guide to VHDL - P.J. Ashenden

Grading Policy

Projects: 3% MP1 13% MP2 25% MP3
Exams: 16% Midterm #1 16% Midterm #2 25% Final
Other: 2% Subjective evaluation

Regrade Policy

Integrity Policy

Late Submission Policy

Late submissions will be subject to the following penalty schedule without exceptions: 15% off for the first day, 10% off for each subsequent day, excluding weekends. No credit will be given to any submissions that are more than 7 days past the due date.

Exam Times and Locations

1st Midterm (time TBA, location TBA)
2nd Midterm (time TBA, location TBA)
Final Dec 16th(wednesday), 7:00-10:00 PM (location TBA)
If you have a conflict, please let me know immediately. These exams have priority over any other commitments that might come up at a later date.