Course Objectives

This course is an intensive introduction to the fundamentals of computer architecture. Relying heavily upon the elementary principles taught in ECE 290 and ECE 390 (old ECE 291), we will discuss the basic design, or architecture, of computing hardware. Computer systems involve architecture design at many levels. We will focus on the instruction set architecture (ISA) level (the interface between the software and computing hardware) and the microarchitecture level (the computing hardware itself). We will examine to some extent, the level above the instruction set (the programming language level) and the level below the microarchitecture (the logic gate level) in order to deepen our understanding of computing systems. This course has a demanding design component; you will implement some of the basic concepts presented in lecture using real hardware design tools.

Contact Information

Instructor

Rakesh Kumar
Office: 208 CSL
E-Mail: rakeshk-at-illinois.edu

Teaching Assitants

Daniel Manjarres (manjarrs-at-illinois.edu)
Dean Glazeski (dean.glazeski-at-gmail.com)
Anthony Brown (anbrown2-at-illinois.edu)

Lecture and Office Hours

Lecture

335 Mechanical Engineering
Tuesday and Thursday
9:30am - 10:50am

Instructor Office Hours

Office hours have not yet been determined.

Course TA Office Hours*

252 EL (EWS) is the main location. We may ask you to meet us at the Grainger Library if 252 EL gets overcrowded.

Dan Manjarres

DayHours
MondayNone
TuesdayAfter Class
WednesdayNone
ThursdayAfter Class
FridayNone
SaturdayNone

Anthony Brown

DayHours
Monday3 - 4pm
TuesdayNone
Wednesday3 - 4pm
ThursdayNone
Friday3 - 4pm
SaturdayNone

Dean Glazeski

DayHours
MondayNone
Tuesday6-ish - ?pm
Wednesday6-ish - ?pm
ThursdayNone
Friday11:00-ish - ?pm
SaturdayNone

* subject to change

Course Essentials

Prerequisites

ECE 290 (or equivalent) and ECE 291 (new ECE 390, or equivalent)

Text

Computer Organization and Design: The Hardware/Software Interface, 3rd Edition - John Hennessy, David Patterson

Other Useful Books

High-Performance Computer Architecture, 3rd Edition - Harold S. Stone
Structured Computer Organization, 4th Edition - Andrew Tanenbaum
The Student's Guide to VHDL - P.J. Ashenden

Grading Policy

Projects: 3% MP1 13% MP2 25% MP3
Exams: 16% Midterm #1 16% Midterm #2 25% Final
Other: 2% Subjective evaluation

Regrade Policy

Integrity Policy

Late Submission Policy

Late submissions will be subject to the following penalty schedule without exceptions: 15% off for the first day, 10% off for each subsequent day, excluding weekends. No credit will be given to any submissions that are more than 7 days past the due date.

Exam Times and Locations

1st Midterm (time 2/18 7-10 pm, location A-K CB214 L-Z CB218)
2nd Midterm (time TBA, location TBA)
Final Dec 16th(wednesday), 7:00-10:00 PM (location TBA)
If you have a conflict, please let me know immediately. These exams have priority over any other commitments that might come up at a later date.

 
“If the automobile had followed the same development as the computer, a Rolls-Royce would today cost $100, get a million miles per gallon, and explode once a year killing everyone inside.”