MP Report Guidelines

Final Report Guidelines

The files below are provided by the TAs to help students with the MPs. The example bit files have worked in the past and should continue to do so. If a given bit file does not work bring this fact to the attention of the TAs.
All bit files use PB_ENTER as a reset switch. Please implement this feature in all of your designs.

Machine Problem 1

MP1 Handout    Update Notes

Machine Problem 2

MP2 Handout    Update Notes    Xilinx EDK BSB Files    Andrew's Notes on Getting ModelSim Working in EDK     Previous Students' Notes on Completing MP2

• Basic Instructions
  • Follow EDK Tutorial
  • Import Custom Core
  • Write ASCII-to-Hex Converter in vhdl. Attach to custom core.
  • Run executable inside Linux to see the hardware-software interaction

• Basic Instructions
  • Create your own CUSTOM pcore
  • Write a VHDL median filter. Accepts 7 inputs and computes the median value
  • Demo design to TA

• Basic Instructions
  • Create your own Linux device driver to interface with your CUSTOM pcore
  • Write a Linux program that initiates a median filter transaction.
  • Demo design to TA
    
    
  Incomplete Driver
  John Kelm Paper on Linux

Machine Problem 3

MP3 Handout    Update Notes

• Basic Instructions
  • 1. Implement in VHDL a component capable of generation of correct VGA synchronization timing.
  • 2. Import your component into the EDK to be able to read from DDR memory.
  • 3. Display the image stored in memory on screen.
  • 4. Watch the web board for support code and helpful hints.
  
  ISE Starter Project with write_sel signal in buffer
  
  Tip 1. Use hierarchy, it is your friend.
  Tip 2. Remember that you will need to read from DDR and write it to your local line buffer.
  Tip 3. Only need to support 640x480@60hz resolution. (Frame buffer is built to support up to 1024x768@72)
  Tip 4. Use ModelSim, ModelSim, ... oh and ModelSim.
  Sample pic to display
  Raw RGB files and DDR loader
  VGA timing specs and illustrative picture

• Basic Instructions
  • 1. Implement a YCrCb to RGB converter and add it to your CP1 design
  • 2. Alter your CP1 design to handle the different word packing in the DDR for YCrCb
  
  Demo code
  RGBtoYCrCb.c

• Basic Instructions
  • 1. Build a DDR burst write block to move data from local buffer into the DDR
  • 2. Parse the YCrCb stream for actual data to write to DDR
  • 3. Program the ADV7183b chip using the I2C protocal
  • 4. Integrate this design into your overall project to have a real time 640x480@60 video displaying on the LCD monitor from the camera
  
  An I2C programming netlist has been provided for you for early debugging. You are responsible for writing your own vhdl to replace this file in the final design
  You may have to handle plb master arbitration with the bus lock signal to make sure your data is written and read without problems from ddr
  Read online documentation to see where real data is in the YCrCb stream.
  TA Solution Bit File
  You may load this bit file on the XUP board to see the expected output.
  

Final Project

Additional files
The zip files contain the pin mappings for both expansion ports. Instructions on which ports to add to your design are included in the UCF files.