ECE443 Lab Schedule

Fall 2009

* Update your kerberos password and read Project #1 before the first lab.

* All sections of ECE443 will meet in Room 268, Everitt lab beginning in Week 2 (8/31 ~ 9/4/2009).

*  Section Q will lag the other sections by one week after Labor Day, 9/7/2009.

	Project #1 (Two Weeks)	Project #2 (Three Weeks)	Project #3 (Four Weeks)	Project #4 (Four Weeks)
Section M (9:00 - 11:50 Tue.)	Start:      Tue. 9/1 Turn in:  Tue. 9/15	Start:      Tue. 9/15 Turn in:  Tue. 10/6	Start:      Tue. 10/6 Turn in:  Tue. 11/3	Start:      Tue. 11/3 Turn in:  Tue. 12/8
Section N (12:00 - 2:50 Tue.)	Start:      Tue. 9/1 Turn in:  Tue. 9/15	Start:      Tue. 9/15 Turn in:  Tue. 10/6	Start:      Tue. 10/6 Turn in:  Tue. 11/3	Start:      Tue. 11/3 Turn in:  Tue. 12/8
Section O (3:00 - 5:50 Tue.)	Start:      Tue. 9/1 Turn in:  Tue. 9/15	Start:      Tue. 9/15 Turn in:  Tue. 10/6	Start:      Tue. 10/6 Turn in:  Tue. 11/3	Start:      Tue. 11/3 Turn in:  Tue. 12/8
Section P (12:00 - 2:50 Thu.)	Start:      Thu. 9/3 Turn in:  Thu. 9/17	Start:      Thu. 9/17 Turn in:  Thu. 10/8	Start:      Thu. 10/8 Turn in:  Thu. 11/5	Start:      Thu. 11/5 Turn in:  Wed. 12/9
Section Q (3:00 - 5:50 Mon.)	Start:      Mon. 8/31 Turn in:  Mon. 9/21	Start:      Mon. 9/21 Turn in:  Mon. 10/12	Start:      Mon. 10/12 Turn in:  Mon. 11/9	Start:      Mon. 11/9 Turn in:  Fri. 12/11

---

ECE443 Syllabus

Week 1 (8/24 - 8/28)       No lab this week

Week 2 (8/31 - 9/4) Project #1   Phase 1      PSpice Simulation of RC circuits                                   

Week 3 (9/7 - 9/11) Project #1   Phase 2      Measurement of Unknown RC Circuits 

Week 4 (9/14 - 9/18) Project #2   Phase 1      Power Supply Design    

Week 5 (9/21 - 9/25) Project #2   Phase 2      Power Supply Simulation      

Week 6 (9/28 – 10/2) Project #2   Phase 3      Power Supply Bench Test   

Week 7 (10/5 - 10/9) Project #3   Phase 1      Digital Logic Circuits: Inverter Simulations    

Week 8 (10/12 - 10/16) Project #3   Phase 2      Digital Logic Circuits: NAND Simulations     

Week 9 (10/19 - 10/23) Project #3   Phase 3      Digital Logic Circuits: Optimization  

Week 10 (10/26 - 10/30) Project #3   Phase 4      Digital Logic Circuits: Bench Test     

Week 11 (11/2 - 11/6) Project #4   Phase 1      Current Source and Difference Pair     

Week 12 (11/9 - 11/13) Project #4   Phase 2      Active Load, Gain Stage, and Output Buffer      

Week 13 (11/16 - 11/20) Project #4   Phase 3      Optimization     

Week 14 (11/23 - 11/27)  Thanksgiving Recess    

Week 15 (11/30 – 12/4) Project #4   Phase 4      Test Circuits    

Week 16 (12/7 - 12/9) Section Q meets on 12/7/2009.

No lab for other sections this week.