Class meeting times:  TTR  11-12.20 am

 Location:                    EngineeringHall 106B8

 Prerequisites:             ECE 290 or CS 231

 Course website:          http://courses.ece.uiuc.edu/ece462/  

 Instructor:                  Shobha Vasudevan

                                    Assistant Professor, ECE Dept.

 Office:                         260, Coordinated Science Laboratory

 Phone:                        217-333-8164

 Email:                         shobhav AT [this university]

 Office hours:              Thursdays, 2-3.30 pm in 260 CSL

COURSE OBJECTIVES

To understand the process of digital logic design in real systems, with respect to performance and functionality constraints; to appreciate the underlying technology as well as the role of logic design in the system design cycle; to enable correct and efficient designs of datapath and control of digital systems when provided with real-life parameters.

SYLLABUS

 Overview of Digital Design

Circuit representations, Process of design in digital hardware, CAD tools, Design goals, Switches, Gates, Logic functions, Theorems of Boolean algebra, K-maps, Canonical forms , Minimization, Boolean function representation

  

 Combinational Logic Design

Duality, Bubbles, Multilevel logic, Complete logic gate sets, XOR, Boolean difference, Shannon decomposition, Boolean minimization, Boolean cubes, Prime implicants, 5 &6 variable functions, Quine Mcluskey method, Heuristic functions, Hazards and Glitches in combinational circuits 

  Sequential Logic Design

Latches and flip flops, R-S latch, J-K latch, D-T latch, Setup and hold time, State, Clocking, Skew, Timing constraints

 Asynchronous circuits

Metasatability, Hazards

  Sequential circuits

State minimization, Registers and counters, ROMs, RAMs (SRAM and DRAM), Designing a simple memory controller

 FSM design

FSM design procedure, Moore and Mealy, Algorithmic state machines, HDLs, One-hot encodings

 Verification and Synthesis

BDDs, Equivalence checking of FSMs, Decomposition and encoding

 Testing

 Technology Mapping

POLICIES AND PROCEDURES

Homeworks will be assigned every other week. They need to be submitted in class. Late submissions will result in a 25% loss in credit and will not be accepted after the solutions have been given.

Missed exams, in exceptional cases, can be administered separately, if provided adequate notice.

The campus-wide policies on academic integrity will be strictly followed and any compromise will not be tolerated.

Grading policies:

Homework               30%

Exam 1                     20%

Exam 2                     20%

Final                         30%

Important dates

Exam 1                     March 10th, 11 am-12.20 am, Class venue

Exam 2                     Apr 16th, 11 am-12.20 am, Class venue

Final                         Not decided

Extra credit will be provided for the best-written class notes in every class that will then be published on the website.

RESOURCES

Textbook                     

Hachtel and Somenzi, Logic synthesis and Verification Algorithms

Reference books

E. J. McCluskey, Logic Design Principles

(Photocopied versions of the entire textbook are available for $14 in the IEEE Store,243 Everitt)

Randy H. Katz, Contemporary Logic Design

Weste and Eshraighan, Principles of CMOS VLSI Design

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