Cadence Inverter Example

Starting Cadence

Enter 'ece482' from your home directory to enter the ece482 work directory.
Enter 'icfb &' to start Cadence.

Setting Up Files

Create a new library

'File-> New-> Library' from Library Manager
Specify a name (ECE482, homework4, etc.)
Choose 'Attach tech library'
Select 'TSMC 0.18u CMOS018/DEEP...' from dropdown list
Click 'OK' to create the library

Select the library that you just created

'File-> New-> Cell View' from Library Manager
Specify a name ('Inverter' was chosen for this example)
Select 'Virtuoso' from dropdown list
Click 'OK'
A layout window should automatically open. If it does not, double click on 'layout' under the 'View' column to open it

Note: If Library Manager window is not present, 'Tools-> Library Manager' will open it.

Setting Options

'Options-> Display' From the layout window you just opened

Set X and Y snap spacings to 0.09
Change display level range from 0 to 32

Not needed here but handy for future projects

'Options-> Layout Editor' and make sure 'Gravity' is off

Creating an Inverter
Please take a min. to familiarize yourself with commands under different menus such as Edit. There are also rules for the sizes of different layers. This will be discussed later.

Select 'nselect' layer in the LSW window (layer select window)
Go back to the layout window
Hit 'r' and create a rectangle (Most commands are also found the Edit Menu)

Objects can be resized later with the stretch 's' command
'k' is a ruler command that is very useful in measuring distances

Repeat this process using Figure 1 as a guide making rectangles of different layors

Size is just a reference and may be larger

Figure 1. Basic NMOS layout shown. Note that the active layer extends under the metal1, poly, and cc layers.

Add a contact to the substrate to act as the body contact

'pselect' with 'active' and 'cc' inside as seen in Figure 2

Make contact from poly gate to metal1

'cc' layer as seen in Figure 2

Note: Alternative to making your own contacts is to hit 'o' and select the contact type and place as a pcell.

Figure 2. Basic NMOS layout with body connection.

Using the above techniques, make a PMOS to accompany the NMOS

The PMOS will need to be inside an nwell
Use Figure 3 as a reference

Figure 3. Basic PMOS layout with body connection.

Add metal1 routing to connect the NMOS and PMOS

Refer to Figure 4

Add Pins

'Create-> Pin'
Enter an appropriate name
Select metal1 from the dropdown list labeled 'Pin Type'
Optional: Select 'Display Pin Name'
Place 4 Pins as seen in Figure 4

Figure 4. Complete inverter with pins. Pins are not normally white but the same as metal1. They were selected to show the reader their locations.

Checking Design Rules

'Verify-> DRC' (design rules check)
Click 'OK' - Default values should work
Any DRC errors will be listed in the CIW window and describe the problem
Fix any errors and repeat until 0 errors are listed

Note: In future projects it is often advisable to run DRC periodically throughout the layout process.
Congratulations! You have now made an inverter.

Extracting

'Verify-> Extract'
Leave the default parameters (Rules file is divaEXT.rul and the Rules Library is TechLib_tsmc02d)
Add parasitics (Needed for later projects)

Click 'Set Switches'
Select 'Extract_parasitic_caps' and click 'OK'

Outputing Netlist

Open the 'extracted' view

See Figure 6

'Tools-> Analog Environment' - This will open another window
In this new window - 'Setup-> Simulator/Directory/Host' and choose 'hspiceS' from the dropdown list and hit 'OK'
'Setup-> Environment' and add the name or your extracted view (normally 'extracted') to the 'Switch View List' right before 'schematic'
'Simulation-> Netlist-> Create Final' will create a netlist for the extracted layout
Either edit this and use it as your netlist or add it as a subcircuit
Example code from an inverter is given below

Figure 6. Location of the created 'extracted' view.

Post Extraction Use

SubCircuit Declaration: subcircuits can be defined by:

.subckt subcircuit_name list_of_subcircuit_nodes

Copied-and-pasted code from the parasitic extraction

.ends

So for our inverter example before, we might get something like this (numbers may be different than yours):


M0 OUT IN VDD VDD  TSMC18DP  L=180.000000682412E-9 W=360.000001364824E-9 
+AD=161.999997834797E-15 AS=161.999997834797E-15 PD=1.25999997635518E-6 
+PS=1.25999997635518E-6 M=1 
M1 OUT IN VSS VSS  TSMC18DN  L=180.000000682412E-9 W=269.999986812763E-9 
+AD=153.900004719321E-15 AS=153.900004719321E-15 PD=1.35000004775065E-6 
+PS=1.35000004775065E-6 M=1 
C2 IN VSS  40.8564E-18 M=1.0 
C3 OUT VSS 65.1744E-18 M=1.0 
C4 VDD VSS  82.575E-18 M=1.0 
C5 VDD OUT  27.1404E-18 M=1.0 
C6 IN VSS  78.9822E-18 M=1.0 
C7 IN VDD  62.3646E-18 M=1.0

This defines a user-defined subcircuit of type INV1. Subcircuits of this type have 4 nodes: IN, OUT, VDD, and VSS. Now, all you have to do when you want to invoke an instance of this inverter is type something like the following:

x1 vIN vOUT 1 0 Inv1

This creates a subcircuit called x1
- The IN gate is connected to node vIN in your spice deck
- The OUT node is connected to node vOUT
- The VDD node is connected to node 1
- The VSS node is connected to node 0
- It is of type Inv1